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Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year
Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Mon, Mar 25 2013
Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!
TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Wed, Feb 20 2013
IBM and Cadence Collaboration Improves Verification Productivity
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Wed, Feb 13 2013
Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Tue, Feb 5 2013
AMS Simulator support for SystemVerilog Math Functions
Hi, I was wondering if it is possible to enable support for the math functions in SystemVerilog (such as $sin) in the AMS simulator. When I try to run a systemverilog file including $sin built-in function in IEEE 1800-2009, I get the following error: sjit = AMP_NOISE*($sin($realtime*2*PI/TNOISE)); Unrecognized...
Posted to
Custom IC Design
(Forum)
by
gintel
on Mon, Feb 4 2013
A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True!
It is January 2013, the year has begun and it is time for my annual 10 year look-back to see how well technology predictions have been implemented or missed (you can find last year's look-back here ). This year's trip into the garage to find my old January IEEE Spectrum issues brought back memories...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Jan 23 2013
Tracking regression results with an SQLITE database
Hi , I would like to keep track of the verification status of my project (verilog/systemverilog) coverage and pass/fail status of tests during the life of the project. Ideally I want to create an SQLITE database to keep track of this since SQLITE is stored in a file which can be archived with the project...
Posted to
Functional Verification
(Forum)
by
andymont
on Tue, Jan 15 2013
Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer
EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 3 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Oct 11 2012
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