Home > Community > Tags > SystemVerilog/OVM
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

SystemVerilog,OVM

  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • Formalizing Multilanguage Mixology For e Users

    Historically it’s been very common for e users to have to mix other programming languages with their e verification environment. Some examples include adding C or C++ reference models, contributing e Universal Verification Components (UVCs) to non- e testbenches, or even interfacing to Matlab models...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 24 2009
  • Are You Playing with a Full Deck?

    A professional gambler confidently place bets because she know the odds, but she would be crazy to play at a table that didn’t use a full deck because the odds change in an unknown way. If you use a simulator that doesn’t enable low-power verification in every test run, you are just as crazy...
    Posted to Functional Verification (Weblog) by Team genIES on Tue, Dec 15 2009
  • OVM Innovation Means Business

    Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Nov 3 2009
  • OVM Tricks and Treats

    Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets! Callback Mechanism...
    Posted to Functional Verification (Weblog) by Team genIES on Fri, Oct 30 2009
  • Using Vera is like Speaking Sumerian – Who’s Left to Understand?

    Just like natural languages, non-standard verification languages can fade away. Sure, ancient Sumerian exists in the Code of Hammurabi , but all modern law is written in living languages. Similarly, verification environments and VIP still exist in Vera, but a shrinking population understands and uses...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Sep 30 2009
  • Verification is a Sprint and a Marathon!

    Verification engineers have updated an old adage to discribe their projects: Verification is both a sprint and a marathon! We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between. Cadence answered that comprehensive call in the Performance...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Sep 30 2009
  • CDNLive San Jose 2009 for the Specmaniac

    Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event is a "hybrid" format of in-person workshops and on-line webinars. As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design &...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 30 2009
  • Xilinx SoC FPGAs Ideal Fit For OVM and MDV

    Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009). In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jun 24 2009
  • VCS Runs OVM -- 2 Years Late, But Welcome None the Less

    Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is buzzing this week about the OVM running on VCS. We first saw a post on the LinkedIn " OVM Professionals Network "on Monday June 15. Today we saw a more detailed posting at IntelligentDV specifically stating a...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Jun 18 2009
Page 4 of 7 (61 items) « First ... < Previous 2 3 4 5 6 Next > ... Last »