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SystemVerilog,Mixed Signal
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Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?
Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 4 2012
Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions
Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept. 20, 2012. While panelists noted progress in mixed-signal design tools and flows, they pointed to a number...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 1 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog...
Posted to
Mixed-Signal Design
(Weblog)
by
PrabalB
on Fri, Mar 30 2012
UVM: "Everything that Can be Invented Has Been Invented" Not True!
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Jan 26 2012
Webinar Report: Power-Aware Mixed-Signal Verification
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions
Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 19 2012
Will Evolving Language Standards Address Mixed-Signal Verification Problems?
Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom...
Posted to
Custom IC Design
(Weblog)
by
Raggie
on Mon, Apr 18 2011
DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs
Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
DVCon: Showcasing The Cadence Passion For Verification Excellence
Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Feb 22 2010
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