Home > Community > Tags > SystemVerilog/IUS/OVM/functional verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

SystemVerilog,IUS,OVM,functional verification

  • Get Started on UVM-e with Free Introductory Video Tutorials

    One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...
    Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
  • type parameter override

    Does NC support type parameter overrides? If not, why not? I'm attempting to use an interface wrapper with a typed parameter to pass interfaces to the drivers/monitors. But I get this error during compile: typedef virtual cllp_if #(.DW(16), .EW(6), .AW(14)) cllp_if_t; IfWrapper #(cllp_if_t) if_wrapper;...
    Posted to Functional Verification (Forum) by hab94 on Wed, Jul 21 2010
Page 1 of 1 (2 items)