Home > Community > Tags > SystemVerilog/IES/Simulation acceleration
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

SystemVerilog,IES,Simulation acceleration

  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
  • Verification is a Sprint and a Marathon!

    Verification engineers have updated an old adage to discribe their projects: Verification is both a sprint and a marathon! We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between. Cadence answered that comprehensive call in the Performance...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Sep 30 2009
Page 1 of 1 (2 items)