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SystemVerilog,Functional Verification

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration Session: 5T on Thursday, Feb. 28 th from 8:30AM - 12:00PM For more details on the debug tutorial, click here This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most...

Posted to Functional Verification (Weblog) by Karnane on Wed, Feb 20 2013
Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...

Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes. Ports in general, and Indexed ports specifically, are static objects...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Oct 9 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 8 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012

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SystemVerilog,Functional Verification

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb. 28th!

Improve Debug Productivity - SimVision Video Series on YouTube

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Using pli_access for Stubless Indexed Ports

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)