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SystemVerilog,Accellera

IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 3 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...

Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 11 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 27 2012
2011 EDA Standards Update and 2012 Forecast

As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 21 2011
Archived Webinar: Bringing SystemC and C/C++ Models into UVM

If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 7 2011
Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative title "UVM and the Death of SystemVerilog." That sure raised some eyebrows here at Cadence and elsewhere, leading to a flurry of tweets debating several of JL's contentions. I was tempted to join in the...

Posted to Functional Verification (Weblog) by tomacadence on Thu, Sep 15 2011
Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom...

Posted to Custom IC Design (Weblog) by Raggie on Mon, Apr 18 2011
DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs

Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011

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SystemVerilog,Accellera

IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

2011 EDA Standards Update and 2012 Forecast

Archived Webinar: Bringing SystemC and C/C++ Models into UVM

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Will Evolving Language Standards Address Mixed-Signal Verification Problems?

DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs