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The Facts: Why Accelerated VIP Is Needed for SoC Verification
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...
Posted to
Functional Verification
(Weblog)
by
PeteHeller
on Tue, May 15 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
Modeling Large Memories in SystemC
Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as 0x40000000, or 1 Gb. Thinking about a SystemC model...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Apr 13 2012
Differentiation Through Hardware is Not Going Away
Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Mar 5 2012
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards
How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 27 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems
The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Thu, Feb 23 2012
The Zynq Virtual Platform: Not Just for Pre-Silicon
One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable for software development. Last week I was talking...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Tue, Feb 7 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 22 2012
compilation error in ncsc_run
Hi, I am facing the following compilation error ---------------------------- building library model.so ld: cannot find -lz collect2: ld returned 1 exit status make: *** [model.so] Error 1 ncsc_run: *E,TBBLDF: Failed to build test library ./libmodel.so ----------------------------------- Is there any...
Posted to
Functional Verification
(Forum)
by
ravi999
on Wed, Jan 18 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
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