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SystemC,Mixed-Signal,Incisive

  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on 02-25-2011
  • SystemC AMS – A New Proposal For Mixed-Signal Verification

    In an effort driven by European semiconductor companies and universities, the Open SystemC Initiative ( OSCI ) last week announced the first version of the SystemC analog/mixed-signal language standard, AMS 1.0. Since Cadence is the industry leader in mixed-signal design and verification, and is strongly...
    Posted to Industry Insights (Weblog) by rgoering on 03-18-2010
  • Adam’s Verification Top 10 In '10

    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on 12-29-2009
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