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SystemC,High-level Synthesis,System Design and Verification

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 13 2012
High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 15 2011
IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...

Posted to System Design and Verification (Weblog) by Jack Erickson on Fri, Aug 12 2011
De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Feb 3 2011
SystemC: It's Neither Complicated Nor Belligerent!

I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons (increased verification productivity, broader micro-architecture exploration, easier re-use, etc). However he was concerned that the learning curve for his team would be too...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 24 2011

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SystemC,High-level Synthesis,System Design and Verification

C-to-Silicon 12.2 Available for Your Holiday Shopping List

High Level Synthesis for a Control-Dominated Design?

IP Cannot be an Efficient Abstraction Level Without SystemC!

De-Mystifying SystemC: What is TLM?

SystemC: It's Neither Complicated Nor Belligerent!