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SystemC,ESL

CircuitSutra Q&A – What It Takes To Develop SystemC TLM Models

SystemC transaction-level models greatly speed design and verification, but they're not easy to develop. CircuitSutra (Noida, India) is a Cadence System Realization Alliance partner that provides SystemC modeling services for virtual platforms, high-level synthesis, and verification. In this interview...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 9 2010
Webinar by XtremeEDA on system realization on September 8th

The first webinar in the series of webinars organized by Cadence with the System Realization Alliance partners is by XtremeEDA on September 8th at 10AM Pacific time. To register click here . About the Webinar Designing integrated circuits from RTL brought about a revolution in semiconductor design about...

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by TeamESL on Sun, Sep 5 2010
Imperas Interview: Connecting Virtual Platforms To HW/SW Verification

Imperas is a provider of virtual platform technology and a member of the new Cadence System Realization Alliance . Imperas has also been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions . Simon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 12 2010
Brian Bailey: Building Towards A Cohesive ESL Flow

Plenty of niche tools fall under the electronic system level (ESL) label, but putting them together into a cohesive flow has been elusive. At the recent Design Automation Conference, consultant Brian Bailey (and blogger at techbites.com ) described how he's been working with Cadence on a flow that...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jul 6 2010
What Language Is Best For High Level Synthesis?

I was not expecting the last panel on the last day of the Design Automation Conference to be well attended, but it was - along with animated discussions and a long line of audience members waiting to ask questions. It turns out that a lot of people were interested in the panel's title: "What...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 30 2010
Specman, e, and EDA360

The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010
DVCon "Day 0" - Quick Report From SystemC Day

If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points. Here is a brief video interview with my colleague Steve Svoboda on the day's events...

Posted to Functional Verification (Weblog) by jvh3 on Mon, Feb 22 2010
Quiet Before The Storm? And What to Expect at DVCon 2010

In the last couple weeks Mentor did an about-face and decided to embrace SystemC ( I told you that would happen! ), and then Synopsys threw down the gauntlet and decided to buy two Virtual Protoyping companies. Supposedly, the word on the street is they are preparing to buy a high-level synthesis company...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Mon, Feb 22 2010
Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models encounter unknowns propagated from shutdown blocks...

Posted to Functional Verification (Weblog) by Team genIES on Thu, Jan 28 2010
A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against the main verification technology-specific observations...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Jan 28 2010

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SystemC,ESL

CircuitSutra Q&A – What It Takes To Develop SystemC TLM Models

Webinar by XtremeEDA on system realization on September 8th

Imperas Interview: Connecting Virtual Platforms To HW/SW Verification

Brian Bailey: Building Towards A Cohesive ESL Flow

What Language Is Best For High Level Synthesis?

Specman, e, and EDA360

DVCon "Day 0" - Quick Report From SystemC Day

Quiet Before The Storm? And What to Expect at DVCon 2010

Low-Power Verification With SystemC - The Great Unknown

A Look Back On 2009 (Before Hazarding Predictions For 2010)