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How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
“Product Creation” Gives EDA a Broader Focus
One term you are likely to hear from Cadence in 2013 is "product creation." A key message in the Cadence Systems and Software Group (SSG), product creation looks beyond chip or board design and considers the entire end product, including software applications, mechanical enclosures, and the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 4 2013
DAC 2012: Users Cite Experiences With Hardware/Software Co-Development
Hardware/software co-development tools such as virtual prototyping, emulation, and FPGA-based prototyping are in use today and are making a difference. That was the message behind a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 5, where two users described their experiences...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jun 17 2012
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 22 2012
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 21 2011
Hot Topic Revisited: System-Level Design and a “New Class” of Engineer
Six months ago I wrote a blog post that considered the question, Is System-Level Design Creating a New Class of Engineer? Since then an ongoing discussion in the LinkedIn electronic system level (ESL) design group has added some new perspectives not considered in my original blog post. To quickly recap...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 6 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation
A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 14 2011
Q&A: A Closer Look at the Cadence Virtual System Platform
Cadence took a significant step into a new marketplace with the recent introduction of the Virtual System Platform , a virtual prototyping environment that supports architectural-level, pre-RTL software development and debugging. The Virtual System Platform is part of the tightly integrated System Development...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 25 2011
Panelists: A Reality Check on Hardware/Software Co-Design and Co-Verification
Is hardware/software co-development ready for prime time? Yes, but much remains to be done, according to panelists at the May 12 EE Times System on Chip "Virtual Event." Panelists discussed hardware/software partitioning, benefits of co-design and co-verification, barriers to adoption, what's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 16 2011
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