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Send Yourself A Copy
System Design and Verification
787
abstraction
Acceleration
architect
architectural
ARM
C
C to Silicon
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Virtualization and Simulation Roundtable
A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that became clear right away is there are way too many...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Tue, Oct 13 2009
Upcoming ARM Techcon3 or is it Techcon Cubed?
The annual ARM Developers' Conference has been renamed ARM techcon3 , or maybe it is ARM techcon cubed. It will be held October 21-23 at the Santa Clara Convention Center. I'm hoping to get to the keynote by Cypress Semiconductor President and CEO, T. J. Rodgers. I worked at Cypress (a long time...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, Sep 17 2009
A Classification of ESL - High Level Synthesis Tools
These days, there is a lot of talk of what the next design methodology for Digital Systems will be and how this methodology will be the replacement of RTL Synthesis. The term ESL (Electronic System Level) is used as a general term for the new wave of modeling and synthesis for digital systems. We have...
Posted to
System Design and Verification
(Weblog)
by
TeamESL
on Thu, Aug 6 2009
Day 1 of DAC is a Wrap
Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis to San Francisco. It seems the fine Northwest aircraft I was on suffered a tripped circuit breaker that led to a relay that had to be replaced. I'm not convinced the aging bird doesn't have vacuum tubes...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Tue, Jul 28 2009
North American SystemC User's Group Co-Located at DAC 2009
We've been hearing about SystemC for a while. It's a great language! What's it great for? Well, you can find out from other users at the coming user group meeting co-located with DAC in San Francsico. This year promises to be full of excitement as the emergence of TLM 2, and many product...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Fri, Jul 17 2009
TLM-Driven Design and Verification Solution
At this week's CDNLive! Japan we made an important press release announcement about our new TLM-driven Design and Verification Solution, and delivered the first Techtorial covering the technology and methodology. The solution combines C-to-Silicon Compiler (CtoS) , Incisive Enterprise Simulator ...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Wed, Jul 15 2009
Industry Standard SystemC is What Designers Want
This past Monday saw not one HLS related announcement but two...this space is really heating-up! Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new features. Today, I'll focus on Catapult, since...
Posted to
System Design and Verification
(Weblog)
by
SteveSvoboda
on Fri, Jul 3 2009
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