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System Design and Verification
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Zynq
Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
There are two choices for how to handle USB devices in a virtual platform. A USB device can be modeled using C/C++ programming, or a physical USB device can be plugged into a computer and attached to the simulator. The Xilinx QEMU for Zynq uses physical USB devices. The Cadence SystemC Virtual Platform...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, May 24 2012
How Debug Breakthroughs are Enabled by In-Circuit Acceleration
We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit acceleration capabilities to our System Development...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, May 16 2012
American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working On!
I think all of us engineers have faced at one point or another the need to explain to our parents or friends what we are actually working on. Hey Mom, EDA is where electronics begins! Without us electronics would not change our day to day lives ... Punctually for Mothers day, which I spent with my Mom...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Mon, May 14 2012
Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox
In my last blog post , I covered three frequently asked questions about using the Xilinx Zynq-7000 Virtual Platform as a VirtualBox appliance. Today, I'll cover the next most frequently asked question. It is related to simulation performance. This should not be considered an official benchmark as...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Mon, May 7 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems
The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...
Posted to
System Design and Verification
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by
fschirrmeister
on Thu, Feb 23 2012
Creating the Zynq Virtual Platform, Including Errata
Although I have never contributed any code to the Linux kernel, the headline We are all Linux developers now on linux today caught my eye. One of the things that amazes me is how many embedded products use Linux and how they deal with all of the complexity. Nearly every product has similar but different...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Fri, Jan 6 2012
Ubuntu Updates for 2012
I'm overdue to provide an update on how to run Virtual System Platform (VSP) and Incisive on the latest version of Ubuntu . My last article was very helpful to many people and users provided additional insight about what worked for them. Just before the holiday break we delivered our latest version...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Mon, Jan 2 2012
High Level Synthesis for a Control-Dominated Design?
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 15 2011
Equine Anatomy, Pax Romana and the Reach of Standards
At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough (Vice-President of Design Technology and Automation...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Dec 14 2011
Parallel Compilation for SystemC
One of the most common complaints about SystemC is that it takes too long to compile. I tend to agree that it does take longer to compile compared to C or Verilog. The primary reason is that SystemC is a somewhat complex set of libraries built on top of C++ and is compiled with g++. Almost every programming...
Posted to
System Design and Verification
(Weblog)
by
jasona
on Thu, Nov 17 2011
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