Home > Community > Tags > Synthesis
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Synthesis

  • Propagate a clock from .LIB of a block
    Hello all, I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated...
    Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012

  • The Technology Behind Encounter 11.1 – Physical Aware Front End Design
    In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 6 2012

  • TLU support for RC?
    Hi, is there a possibility in Cadence RC to use TLU or TLU+ data for synthesis? Alex'
    Posted to Logic Design (Forum) by Alex Kli on Wed, Feb 8 2012

  • RTL compiler - synthesis
    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012

  • User View: “Multi-Mode” Synthesis Approach Includes Power Optimization
    Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012

  • Synthesis User Panel: Power Dominates Front End Design
    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011

  • How Logic Synthesis is Changing
    You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 14 2011

  • ARM TechCon Paper: “Tips and Tricks” for Cortex-A15 Designs
    The Cortex-A15 MPCore, ARM's most advanced processor, requires an optimized tool flow and design methodology to meet power, performance and area goals. A paper at the recent ARM TechCon conference showed how Texas Instruments, in collaboration with Cadence and ARM, successfully pioneered one of the...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 2 2011

  • Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers
    Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 18 2011

  • Synthesizing 'x'
    Hi, look at the following code: always @(*) begin o = 2'bxx; if (a) o = 2'd0; else if (b) o = 2'd1; else if (c) o = 2'd2; else if (d) o = 2'd3; end signal o is DC (don't care) if none of the inputs (a,b,c,d) is asserted. I used the 2'bxx value because (1) it's easier to...
    Posted to Logic Design (Forum) by Tzachi Noy on Mon, Jul 11 2011
Page 3 of 7 (64 items) < Previous 1 2 3 4 5 Next > ... Last »