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  • Pspice model errors in Virtuoso

    Hi Guys I am trying to simulate MAX9643U and EL7202 (using their Pspice models) as a part of my design, in Virtuoso. While I have reviewed many similar problems and solutions in this informative website, I still can not overcome the errors. 1) MAX9643U (the model is available here: http://www.maximintegrated...
    Posted to Custom IC Design (Forum) by Politekniko on Fri, Jan 17 2014
  • Modify netlist of a block and resimulate (CDL.... CDF....)

    Hello everyone, I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a spectre view before by following this tutorial:
    Posted to Custom IC Design (Forum) by cozdag on Sat, Dec 28 2013
  • Spectre XPS – Cadence Reinvents FastSPICE Simulation

    Last year I wrote a blog post suggesting that FastSPICE simulation technology is "hitting the wall." A new approach is clearly needed, and Cadence is responding this week (Oct. 9, 2013) with Spectre XPS (eXtensive Partitioning Simulator), a FastSPICE simulator that sets new milestones for speed...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 9 2013
  • Spice model in Spectre

    Hello, Andrew! I think, I have similar problem simulating the following model in spectre: .SUBCKT IPD100N06S4 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Zthtype=0 Ls=1.5n Ld=1n Lg=3n .PARAM Rs=659u Rg=1.3 Rd=50u Rm=180u .PARAM Inn=90 Unn=10 Rmax=3.5m gmin=60 .PARAM RRf=390m Rrbond...
    Posted to Custom IC Design (Forum) by Runner on Fri, May 17 2013
  • Mixed Signal Technology Summit Proceedings Now Available

    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
    Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
  • SPICE Correlation Made Easy by Encounter Timing System (ETS)

    Hello, and welcome to my first blog! As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing...
    Posted to Digital Implementation (Weblog) by MJ Cad on Mon, Dec 10 2012
  • CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

    We have been talking about low power simulation and the Common Power Format (CPF) for five or six years now. It’s become popular in most digital designs thanks to a mature methodology and design flow. However, more and more SoC designs are coming up with mixed-signal content. How will low power...
    Posted to Mixed-Signal Design (Weblog) by Qingyu Lin on Mon, May 23 2011
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • SPICE Pioneers Reveal History of 40-Year-Old Circuit Simulator

    There aren't many currently used EDA tools that are celebrating 40 th anniversaries this year, but the SPICE circuit simulator, first released by the University of California in 1971, is. SPICE creators and innovators spun compelling and amusing tales of the development of the venerable circuit simulator...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 24 2011
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