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Specman,vr_ad,uvm,Functional Verification

  • UVM e vr_ad -- Specman Read/Write Register Enhancements

    If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence 2. Add a field of the type of the register you want to access 3. In the body() , call the read/write_reg For example...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Nov 23 2012
  • UVM - 10 Years in the Making ...

    In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
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