Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Specman/e/OVM-e/Functional Verification
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Specman,e,OVM-e,Functional Verification
accellera
Accellera VIP TSC
AMS
AOP
API
Aspect Oriented Programming
Avi Behar
CDNLive
CDV
ClubT
coverage driven verification (CDV)
Coverage-Driven Verification
DAC
EDA360
eRM
ESL
events
funtional verification
Gauss
hvl
HW/SW
IEEE 1647
IES
IES-XL
IEV
Incisive
Incisive Enterprise Simulator (IES)
IntelliGen
IP
ISX
ISX (Incisive Software Extensions)
job postings
Jobs
Kaberi
Matlab
MDV
methodology
metric driven verification (MDV)
Mixed Signal Verification
Multi-domain verification: HW/SW co-verification
multi-language
N-queens
Object Oriented Programming
OOP
Open Verification Methodology
OVM
OVM e
OVM ML
OVM SV
OVMWorld
performance
Register Package
Rubik's Cube
sequences
simulation
specman elite
specman job postings
System Verification
SystemC
SystemVerilog
team specman
tech tips
temporal expressions
Testbench simulation
Trailblazer
uvm
Verification methodology
VHDL
VIP
vr_ad
when sub-typing
If Only Carl Friedrich Gauss had IntelliGen in 1850
The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia ( http://en.wikipedia.org/wiki/Eight_queens_puzzle .) The challenge is to place N queens on...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Aug 18 2011
e Verification Job Postings We’ve Seen
Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Aug 6 2010
Specman, e, and EDA360
The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jun 8 2010
UVM - 10 Years in the Making ...
In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...
Posted to
Functional Verification
(Weblog)
by
mstellfox
on Mon, May 17 2010
Performance-Aware e Coding Guidelines – Part 5
In this last segment of the series on performance-aware coding, allow me to share with you two tips on improving the performance of Temporals. Temporals Performance Tip 1: Setup a "Synch Unit" If you don't already use a synch unit - I recommend you setup one up now. Here's why: the...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 28 2009
Performance-Aware e Coding Guidelines – Part 4
Specman 8.2s3 contains a new API to the sequence driver that enables users to improve the performance of stimulus creation. With this API you can create stimulus items in an efficient manner, and reduce the number of context switches between the sequence and its driver. For example, instead of many generation...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Apr 16 2009
Performance-Aware e Coding Guidelines – Part 2
Building on Part 1 where I talked about the “do’s and don’ts” of List performance , in this segment on performance-aware coding I’ll show you some memory saving tips. We base this segment on base types (geeky pun intended) … Base types extensions Creating base classes...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Apr 6 2009
IMPORT Guidelines For e, Part 1
[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger] Hi, my name is Avi Behar and for the past eight years I’ve been supporting Specman users from Allentown to Yokohama (any Specmaniacs at a location starting with "Z"? I’m coming!). If you are reading this and...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Mar 19 2009
New OVM-e Testflow Features Introduce Increased Automation
Hi All, With the release of the OVM- e library, there are now many new features available for users to take full advantage of. I would like to discuss one new feature that, when introduced into a users environment, allows for much greater automation and control over a given simulation run. The e language...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Feb 25 2009
Page 1 of 1 (9 items)