	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Specman,e,Functional Verification

Accellera VIP TSC
AF
AMIQ
AMS
AOP
API
apps
Aspect Oriented Programming
C
Cadence VIP portfolio
CDNLive
CDV
CFS Vision
ClubT
coverage driven verification (CDV)
Coverage-Driven Verification
DAC
debug
DVcon
DVCon 2013
DVT
e language
eclipse
EDA
EDA360
eDoc Specman e
Enterprise Manager
Enterprise Planner
Ericsson
eRM
ESL
eVC
events
formal
Formal Analysis
FOSS
Gauss
Goss
hvl
HW/SW
IDE
IEEE 1647
IES
IES-XL
IEV
IFV
Incisive
Incisive Enterprise Simulator (IES)
Industry Insights
IntelliGen
ISX
ISX (Incisive Software Extensions)
Low Power
macros
Matlab
MDV
MDV techtorial
methodology
metric driven verification (MDV)
Mike Stellfox
Mixed Signal Verification
Multi-domain verification: HW/SW co-verification
multi-language
Object Oriented Programming
OOP
Open Verification Methodology
OVM
OVM e
OVM ML
OVM SV
OVM-e
OVMWorld
performance
Plan and metrics management
sequences
simulation
SimVision
SoC
Specman e
specman elite
SVA
System Verification
SystemC
SystemVerilog
team specman
tech tips
techtorial
testbench
Testbench simulation
TLM
Trailblazer
Twitter
uvm
verification
Verification methodology
verification strategy
VHDL
VIP
vr_ad
when sub-typing

DVCon 2013: Functional Verification Is EDA’s “Killer App”

With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...

Posted to Functional Verification (Weblog) by jvh3 on Sun, Mar 10 2013
Bidirectional has() and count() List Pseudo-Methods

Hi. As of the 11.1 release, the list.has() and list.count() list pseudo-methods can be treated as bidirectional constraint operators. In 11.1, list.has() and list.count() are solved unidirectionally by default. To ensure that these pseudo-methods are solved as bidirectional expressions, set the config...

Posted to Functional Verification (Forum) by IonutC on Tue, Mar 5 2013
DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
Re: time between two events

you have sys.time and sys.realtime. You can log the time value when an event happens (using for example and on block) and next time you can calculate the delta. -hannes

Posted to Functional Verification (Forum) by hannes on Thu, Oct 11 2012
Error : Overflow, divider cannot be zero

Hi All, I am using a vr ahb (eVC) and i get this error "Overflow, divider cannot be zero" . I have no clue how to debug this error. Coud anyone please throw some light on thsi error?

Posted to Functional Verification (Forum) by bharathwajan on Wed, Jun 20 2012
Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 17 2012
Webinar Seeks to “End the Debate” – e or SystemVerilog?

Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia ( http://en.wikipedia.org/wiki/Eight_queens_puzzle .) The challenge is to place N queens on...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Aug 18 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API

Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Jun 22 2011

Page 1 of 10 (96 items) 1 2 3 4 5 Next > ... Last »

Popular Tags

Email

Share

Subscribe

Contact Us

Specman,e,Functional Verification

DVCon 2013: Functional Verification Is EDA’s “Killer App”

Bidirectional has() and count() List Pseudo-Methods

DVCon 2013 for the Specmaniac

Re: time between two events

Error : Overflow, divider cannot be zero

Get Started on UVM-e with Free Introductory Video Tutorials

Analyzing Error Reports When Specman Crashes

Webinar Seeks to “End the Debate” – e or SystemVerilog?

If Only Carl Friedrich Gauss had IntelliGen in 1850

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API