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Specman,e language,simulation

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic load and reseeding. This allows the user to run the simulation up to a certain point (often until right after reset) and save the simulation. The user can then restore the simulation and run many different tests either by...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 12 2013
DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes. Ports in general, and Indexed ports specifically, are static objects...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Oct 9 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Aug 15 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 2 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...

Posted to Functional Verification (Weblog) by teamspecman on Tue, May 22 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...

Posted to Functional Verification (Weblog) by teamspecman on Fri, May 11 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012

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Specman,e language,simulation

Develop for Debugability – Part 1

Using the ‘restore -append_logs' Feature

DVCon 2013 for the Specmaniac

Using pli_access for Stubless Indexed Ports

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Tips on Writing Macros in Specman e Language

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification