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Tips on Writing Macros in Specman e Language
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, May 22 2012
UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Mon, May 21 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, May 11 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 24 2012
Type conversion from hex String to uint (32 bits) in Specman e
Hi All, I am trying to read a file which has address and data in hex separated by space as shown below : 0001FF 0x47295784 I am having problem with converting the hex string 0001FFF to uint 32 bits and send this to my driver for further action. I have tried the following syntax from the cadence docs...
Posted to
Functional Verification
(Forum)
by
bharathwajan
on Wed, Apr 18 2012
Analyzing Error Reports When Specman Crashes
One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 17 2012
Non HTML coverage report generation using E-manager
Hi, After my specman regression is complete, I am trying to generate a non-html coverage report using E-manager. When i explored the E-manager tool, I could only see HTML report generation options. Is it not possible to generate non-html reports? or atleast any work around to generate one from html?...
Posted to
Functional Verification
(Forum)
by
bharathwajan
on Sun, Feb 19 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
Re: assertion in e
Yes, the event has nothing whatsoever to do with the expect. every event occurs when it is emitted or if the temporal expression of the EVENT succeeds.you seem to think that the name associates the event with the expect. This is not the case. If you want an event on a temporal expression just do "event...
Posted to
Functional Verification
(Forum)
by
hannes
on Tue, Dec 20 2011
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