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“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
Webinar Seeks to “End the Debate” – e or SystemVerilog?
Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 21 2011
Free Webinars Explore Advanced Functional Verification Techniques
UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 15 2011
Support for e Language Macros in Amiq DVT Tool
DVT ( D esign and V erification T ools), a product offering from a 3rd party vendor, AMIQ , is for verification engineers working with e and SystemVerilog who are dissatisfied with the limitations of plain text editors and plain text searches (grep) when reading, writing or understanding source code...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 25 2011
Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog
A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: " Is e or SystemVerilog Best for Constrained-Random Verification? " This blog post has received much positive feedback from other Specman...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 18 2011
My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your Reason?
I'd like to share with you a story from many, many, many moons ago when I first evaluated e as a potential verification language solution for the company I was working for. At the time, our verification group was using the basic Verilog behavioural constructs for verification (memories to represent...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Jan 12 2011
2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More
If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Tue, Nov 9 2010
Users Employ Specman Constrained-Random Verification for Complex IP
Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe (Germany), and Sarmad Dahir, ASIC designer at Ericsson (Sweden),...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Sep 3 2010
Advanced Option Brings New Features to Specman/e Users
Great news for Specmaniacs -- a new Specman Advanced Option is being announced at the Design Automation Conference (DAC) for Specman/ e users. Three key functionalities in this Option will be: Multi-core Compilation - Close to Nx (N= # cores) speedup in compilation time. Re-Seed/Dynamic Load - Allow...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Jun 11 2010
Specman, e, and EDA360
The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jun 8 2010
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