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Specman,OVM,eRM

Get Started on UVM-e with Free Introductory Video Tutorials

One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...

Posted to Functional Verification (Weblog) by teamspecman on Thu, May 24 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
Webinar Seeks to “End the Debate” – e or SystemVerilog?

Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API

Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting e RM, OVM, and now the full production UVM. At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Jun 22 2011
UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been...

Posted to Functional Verification (Weblog) by mstellfox on Mon, May 17 2010
Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting the e language and/or Specman technology, allow us to direct your attention to this interview of Cadence Verification VP Mitch Weaver (who never worked for Verisity, BTW) by industry analyst Richard Goering. As...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 16 2010
DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
1st Anniversary Of The Team Specman Blog!

Specmaniacs rejoice: today is the 1st anniversary of the launch of this blog!!! To commemorate the occasion, allow us to highlight the top 5 posts (out of 72 total!) from the past year, AND give a shout out to the Specmaniac websphere with a roll-up of Specman and e language oriented online resources...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Dec 10 2009
CDNLive San Jose 2009 for the Specmaniac

Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event is a "hybrid" format of in-person workshops and on-line webinars. As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design &...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 30 2009
Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following me: Before discoursing on this unusually public display of affection, allow me to take a step back and announce that I've started to tweet on Twitter . While initially put off by the apparent solipsism embedded...

Posted to Functional Verification (Weblog) by jvh3 on Mon, Jun 29 2009

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Specman,OVM,eRM

Get Started on UVM-e with Free Introductory Video Tutorials

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Webinar Seeks to “End the Debate” – e or SystemVerilog?

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open API

UVM - 10 Years in the Making ...

Cadence Exec: Why Cadence is Comitted to e/Specman

DVCon 2010 For The Specmaniac

1st Anniversary Of The Team Specman Blog!

CDNLive San Jose 2009 for the Specmaniac

Yikes - Synopsys is Following Me!