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Specman e ports

  • Type conversion from hex String to uint (32 bits) in Specman e

    Hi All, I am trying to read a file which has address and data in hex separated by space as shown below : 0001FF 0x47295784 I am having problem with converting the hex string 0001FFF to uint 32 bits and send this to my driver for further action. I have tried the following syntax from the cadence docs...
    Posted to Functional Verification (Forum) by bharathwajan on Wed, Apr 18 2012
  • Re: event on combination of VHDL and verilog RTL path

    Hi. Firstly you should not be using tick accesses these days. You should be using simple ports instead, as they have better performance and give less flow problems such as the VHDL/Verilog binding that you're seeing. dma_done_w : in simple_port of bit is instance; keep dma_done_w.hdl_path() == "...
    Posted to Functional Verification (Forum) by StephenH on Thu, Dec 2 2010
  • event on combination of VHDL and verilog RTL path

    Hi All, I am making one event like : event collect_cover_done_e is rise('~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w')@sim; Here the issue i am getting is : *** Error: From NCVHDL adapter: Missing access rights. No read/write access...
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Dec 1 2010
  • vr_ad_file multiple instance

    Hello All, I have a situation where i want to implement 8 instance of some particular reg_file which all have many reg_def and reg_fld. For example : I have 8 instance of one DUT module (TEST0, TEST1,TEST2... TEST8), since its all are the instance so all the instance will have the sets of registers....
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Sep 1 2010
  • Re: canit able to connect the ports

    Hi Muthu, I'm not sure whether I fully understand your question, so let me re-phrase it and see if I got it right. You want to connect the ports of OVC_A to the ports of OVC_B and the ports of OVC_B to the RTL signals? If this is your situation, then in fact you can simply constrain the OVC_A hdl_path...
    Posted to Functional Verification (Forum) by StephenH on Fri, Feb 12 2010
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