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Specman e ports,Specman e,e

  • event on combination of VHDL and verilog RTL path

    Hi All, I am making one event like : event collect_cover_done_e is rise('~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w')@sim; Here the issue i am getting is : *** Error: From NCVHDL adapter: Missing access rights. No read/write access...
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Dec 1 2010
  • vr_ad_file multiple instance

    Hello All, I have a situation where i want to implement 8 instance of some particular reg_file which all have many reg_def and reg_fld. For example : I have 8 instance of one DUT module (TEST0, TEST1,TEST2... TEST8), since its all are the instance so all the instance will have the sets of registers....
    Posted to Functional Verification (Forum) by Ravisinha on Wed, Sep 1 2010
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