Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> SoCs
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
SoCs
abstraction
All Things Analog
AMS
AMS Designer
AMS Verification
analog
analog assertions
analog behavioral models
analog verification
analog/mixed-signal
application-driven
applications
Applicon
apps
ASIC
ASIC/ASSP
Bell Labs
Berkeley
Bhagwan
Binyamini
CAD
Cadence
Calma
CDNLive
CDNLive 2013
CDNLive SV 2013
CEDA
Chang
China
chip design
Coleman
Computer Vision
Conformal
convergence
Cool Verification
Costello
coverage data
coverage metrics
CPF
creators
Daisy
design starts
Designers Guide Consulting
digital verification
DVCon
DVCon 2013
DVcon panel
ECOs
EDA
EDA history
EDA360
EDI
embedded software
Enconcert
formal verification
FPGA
FPGAs
Functional Verification
Ghz Circuits
high-level models
Hogan
IBM
IC Design
ICCAD
Incisive
Industry Insights
integrators
Intel
intent
Intrinsix
IP
J.L. Gray
Japan
low power
mixed signal
mixed-signal
silicon realization
Smith
SoC Realization
software
software apps
software testing
software validation
software verification
SPICE
static analysis
Stone
Synopsys
synthesis
system realization
system-on-chip
systems
systems on chip
Tech on Tour
Teggatz
testbench
verification
Vico
Virtuoso
vision paper
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America
At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Mar 29 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?
If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Mar 1 2013
Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm"
Few people have been as influential in the development of EDA as Alberto Sangiovanni-Vincentelli , professor at the University of California at Berkeley and Cadence board member. At the International Conference on Computer-Aided Design (ICCAD ) Nov. 6, he delivered a presentation that ranged from the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 8 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?
Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 1 2012
All Things Analog – Video Interviews with Experts
John Pierce, product marketing director at Cadence, recently sat down with several analog/mixed-signal design and verification experts for "All Things Analog" video interviews. These short (8-11 minute) video clips offer some good insights into analog verification and simulation, PLL design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 4 2012
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
Ten Key Ideas Behind EDA360 – A Revisit
The EDA360 vision paper was published by Cadence one year ago this week. Since that time, EDA360 has been widely discussed throughout the industry - by partners and competitors alike - whether or not they actually use the term "EDA360" or just talk about the ideas behind it. Over the past year...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 28 2011
Is China Ready for Next Generation Mixed-signal Design?
A Chinese design engineer told me that his manager once told him: "You do not have to have creativity but you must know how to imitate!" This is kind of a reflection of the rapid technology growth in China for the past decade, where many of the technology advancements came from learning the...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Fri, Mar 18 2011
Advanced Mixed-Signal Designs Demand a Unified Methodology
Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Sun, Feb 6 2011
User Interview: Getting “Real” With Mixed-Signal Simulation
Using traditional analog solvers for top-level, mixed-signal SoC simulation is inefficient and impractical. Intrinsix , a design services firm, recently evaluated an alternative solution called real number modeling (RNM). This solution makes it possible to use real numbers in a digital simulation, letting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 2 2009
Page 1 of 2 (11 items) 1
2
Next >