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SoC

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...

Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems

A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new type of IP will be "system driven," and...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 17 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...

Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Mar 5 2012
Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

As president and CEO of Chip Estimate before its 2008 acquisition by Cadence, Adam Traidman has been a front-row observer of the silicon IP business for many years. His company developed the InCyte chip planning tool, which includes an IP database to help designers predict area and performance. Today...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 23 2012
Who Needs 40/100 Gigabit Ethernet SoCs?

Short answer: the cloud. Thanks to cloud computing and cloud applications, data centers are having to manage large data transfers in very short periods of time. System-on-chip (SoC) solutions that support 40/100 Gbit Ethernet (GbE) are now in demand, and for this reason, Cadence today (Feb. 21, 2012...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 21 2012
Digital and Analog Verification – Round Peg in a Square Hole?

Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 9 2012
Panelists: Bridging the Gap Between Analog and Digital Design

Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 1 2012
Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs

Memory is an important part of virtually every electronic system, yet it's increasingly becoming a performance bottleneck. The latest ONFi 3.0 (Open NAND Flash Interface) specification promises to ease this bottleneck for nonvolatile memory. But silicon IP support is needed to facilitate adoption...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 9 2012

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SoC

UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems

UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

Differentiation Through Hardware is Not Going Away

Q&A: Adam Traidman Updates Silicon IP Trends and ChipEstimate.com

Who Needs 40/100 Gigabit Ethernet SoCs?

Digital and Analog Verification – Round Peg in a Square Hole?

Panelists: Bridging the Gap Between Analog and Digital Design

Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs