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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer and partner presentations were scheduled between...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 21 2013
DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 16 2013
How to use the Encounter RTL Compiler Super-Thread with Tivoli Workload LoadLeveler
Hello all, Please I would like to use my Encounter RTL Compiler, later the EDI, to place the parallel synthesis into a HPC cluster. I understand that for this purpose I must use Super-Thread, and that I must configure it using: set_attribute super_thread_servers { machine_names } / In this stage I already...
Posted to
Logic Design
(Forum)
by
lvcargnini
on Tue, May 14 2013
How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
Why Cadence Agreed to Acquire Tensilica – And How It Can Change SoC Design
On March 11, 2013, Cadence announced an agreement to acquire Tensilica, a successful provider and market leader in dataplane processing IP. By providing a more complete solution for system-on-chip (SoC) design, the acquisition will facilitate a new generation of highly differentiated, low-power, high...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 17 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Lip-Bu Tan, Cadence president and CEO, is excited about ongoing innovation within the electronics industry - but he's also aware of challenges such as advanced node lithography, complexity, time-to-market, and rising design costs. In a keynote speech at the CDNLive Silicon Valley conference March...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 12 2013
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions
The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 27 2013
What the 787 Dreamliner Can Teach Us About SoC design
The commercial aircraft industry is at a stage where it innovates at a much slower pace than the chip design industry -- however, we can find some parallels that offer us lessons. The most notably innovative aircraft recently developed is the Boeing 787 Dreamliner . It is the first commercial aircraft...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Feb 20 2013
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