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Webinar Report: Speeding RTL and Gate-Level Simulation
Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 13 2012
iPhone5 Differentiation is Chip Design
In case you may have missed it, Apple recently launched a new iPhone. As per the iPhone launch tradition, it brings with it a lot of excitement over the latest capabilities. Of course we don't know everything until it is actually available, but this latest incarnation has broken all kinds of records...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Sep 19 2012
High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here . His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 26 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
IP Cannot be an Efficient Abstraction Level Without SystemC!
EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Fri, Aug 12 2011
Do You Have a DATE with Software? Cadence Does!
How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in...
Posted to
System Design and Verification
(Weblog)
by
Steve Brown
on Mon, Feb 28 2011
Impressions From A “Virtual” SoC Conference
I attended portions of an EE Times “virtual” system-on-chip (SoC) conference last week, and came away with some observations that I’d like to share. There is some irony here. After years of writing about Cadence and other EDA vendors for EE Times, I am now reporting about an EE Times...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 21 2009
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