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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer and partner presentations were scheduled between...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 21 2013
DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 16 2013
How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
Why Cadence Agreed to Acquire Tensilica – And How It Can Change SoC Design
On March 11, 2013, Cadence announced an agreement to acquire Tensilica, a successful provider and market leader in dataplane processing IP. By providing a more complete solution for system-on-chip (SoC) design, the acquisition will facilitate a new generation of highly differentiated, low-power, high...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 17 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions
The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 27 2013
Cadence Cosmic Circuits Acquisition – Analog/Mixed Signal IP for Advanced Node SoCs
Last week (Feb. 7, 2013) Cadence announced an agreement to acquire Cosmic Circuits Private Limited, a leading provider of analog/mixed-signal IP based in Bangalore, India. Here's some background on this relatively young, fast-growing company, and how its offerings fit into the growing Cadence design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 11 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance
Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
Webinar Report: Speeding RTL and Gate-Level Simulation
Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 13 2012
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM
Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 5 2012
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