Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> SoC/IP
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
SoC,IP
Accellera
AMBA
AMS
Analog
analog assertions
analog/mixed-signal
apps
ARM
assertions
Atrenta
Cadence
CDN Live
CDNlive
CDNLive Silicon Valley
CDNLive!
CDNLive! Silcon Valley
chip estimate
ChipEstimate
ChipEstimate.com
cloud
Co-Design
controller
controller IP
Cosmic Circuits
coverage
co-verification
DAC
DAC 2012
DDR
DDR4
debugging
Denali
Design Automation Conference
design IP
DesignCon
digital
DRAM
DVCon
EDA360
EE Times
embedded software
ESL
Ethernet
Ethernet IP
flash
Functional Verification
hardware/software
hls
Incisive
Industry Insights
integration
IP integration
IP quality
IP Reuse
IP stack
IP Talks
IP Talks!
IP-XACT
John Heinlein
Kapoor
low power
Lund
Martin Lund
memory
memory IP
memory models
mixed signal
Mixed-Signal
Nizic
Open Integration Platform
Panel
PCI Express
PHY
RTL
semiconductor IP
silicon IP
SoC Integration
SoC Realization
software
Sonics
specman
storage
subsystems
synthesis
System Design and Verification
System Development Suite
system on chip
SystemC
Tensilica
TLM
TSMC
UVM
UVM-MS
verification
verification IP
Verilog-AMS
VIP
virtual conference
webinar
wreal
DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information. Now in its 7 th year, IP Talks! includes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 16 2013
How Hardware/Software Co-Development Fuels “Product Creation”
I've written recently about "product creation," a concept that looks beyond the chip or board and considers the requirements of the entire end product, including hardware, software applications, and mechanical enclosures. These requirements ripple down through the design supply chain and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 3 2013
Why Cadence Agreed to Acquire Tensilica – And How It Can Change SoC Design
On March 11, 2013, Cadence announced an agreement to acquire Tensilica, a successful provider and market leader in dataplane processing IP. By providing a more complete solution for system-on-chip (SoC) design, the acquisition will facilitate a new generation of highly differentiated, low-power, high...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 17 2013
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP
Systems on chip (SoCs) are incredibly varied, extremely complex, and based on rapidly changing requirements and specifications, according to Martin Lund, senior vice president for R&D at the Cadence SoC Realization Group. At a keynote speech at the CDNLive Silicon Valley conference March 12, 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 14 2013
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Lip-Bu Tan, Cadence president and CEO, is excited about ongoing innovation within the electronics industry - but he's also aware of challenges such as advanced node lithography, complexity, time-to-market, and rising design costs. In a keynote speech at the CDNLive Silicon Valley conference March...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 12 2013
2013 CES: Top 4 Trends Benefiting EDA
While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Thu, Jan 17 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM
Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 5 2012
Q&A: Cadence VP Martin Lund Brings User Perspective to Semiconductor IP
Martin Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group. He hasn't worked for an EDA company in the past, but 12 years at Broadcom -- most recently as senior vice president and general manager of Broadcom's Network Switching Business -- gave...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 20 2012
IP Talks! Video – ARM’s John Heinlein Cites SoC Success Requirements
John Heinlein, vice president of marketing for the Physical IP division at ARM, believes that an advanced system-on-chip (SoC) design shouldn't be a "leap of faith." In a keynote speech at the IP Talks! sessions at the ChipEstimate.com booth at the Design Automation Conference (DAC 2012...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jul 10 2012
Page 1 of 5 (45 items) 1
2
3
4
5
Next >