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  • TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

    Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate ( CoWoS ) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 4 2012
  • What Is FPGA/PCB Co-Design - And Why Is It Needed?

    You may think that FPGAs are "easy" to design compared to ASICs or SoCs. But just wait until you try putting a large, complex FPGA on a printed circuit board. Several things could go wrong - including pin assignments that don't work in the board layout, signal integrity problems on the...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 5 2010
  • Should IC Designers Worry About Temperature?

    Three years ago I wrote an EE Times article about the growing importance of thermal gradients and thermal analysis at 90 nm and below. That article turned out to be ahead of its time. Today, thermal issues are not among the top few designer concerns at mainstream process nodes. But indications are that...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 21 2010
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