Home > Community > Tags > SoC design/IEEE panel
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

SoC design,IEEE panel

  • IEEE Panel Charts “Top SoC Design Challenges”

    What are the top ten challenges in system-on-chip (SoC) design today? Can virtual platforms, cloud computing, and fully depleted silicon-on-insulator (FD-SOI) be part of the solution? Experts discussed these points April 8, 2014, in a panel organized by the IEEE Computer Society of Silicon Valley (IEEE...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 9 2014
Page 1 of 1 (1 items)