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Simulation,metric-driven verification

DVCon 2013 Expert Panel: How to Succeed with Verification Planning

While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 5 2013
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
Digital and Analog Verification – Round Peg in a Square Hole?

Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...

Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 9 2012
1st Anniversary of the Team Verify Blog!

Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!! To commemorate the occasion, allow us to highlight the top 5 posts (out of 25 total!) from the past year. Without further adieu, in ascending order of web hits and comments received ... #5 - "Everything Assertion Based"...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Apr 11 2011
The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification: How good are my formal constraints? (Addressed in Part 1 ) How good is my verification proof...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Feb 14 2011
What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Jan 11 2011
Q&A: Formal Verification in 2011 – Update and Forecast

Alok Jain, distinguished engineer at Cadence, directs the company's R&D efforts in formal verification. When he recently visited Cadence San Jose headquarters, we talked about the status of formal verification technology today and trends developing for 2011. Specifically, we talked about formal...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 2 2011

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Simulation,metric-driven verification

DVCon 2013 Expert Panel: How to Succeed with Verification Planning

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Digital and Analog Verification – Round Peg in a Square Hole?

1st Anniversary of the Team Verify Blog!

The Role of Coverage in Formal Verification, Part 3

What Does Silicon Realization Mean for Verification Engineers?

Q&A: Formal Verification in 2011 – Update and Forecast