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Simulation

  • ADE hangs up when java is running

    Dear Cadence-Experts, I have a problem with the ADE (Analog Design Environment) running within a newly installed Cadence software (IC 6.1.3, MMSIM 7.01, IUS 8.10 under RedHat 4 on Intel Core i7 CPU 950). Problem scenario 1: * A quick way to trigger the problem is to try to change the "Project Directory"...
    Posted to Custom IC Design (Forum) by Michael2010 on Thu, Nov 25 2010
  • Broadcom Presentation Shows Value of Transaction-Based Acceleration

    Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal , showed evidence that simulators are running out of steam for system level simulations. At Broadcom, simulators certainly...
    Posted to System Design and Verification (Weblog) by rmathur on Tue, Nov 16 2010
  • New Fast Envelope in MMSIM10.1 is *Really* Fast and Accurate!

    Traditionally, envelope analysis is used to simulate circuits with modulated inputs. Envelope analysis is much faster than transient simulation, and is used for simulating spectral regrowth. Regular envelope analysis is "brute force" transistor-level simulation: Simulation time for traditional...
    Posted to RF Design (Weblog) by Tawna on Mon, Nov 15 2010
  • Cadence Low-power Verification: Tear Down These Walls

    You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation? Got it. Mixed-signal? Yep. Every team with fingers in the power intent? For sure. Siicon...
    Posted to Low Power (Weblog) by Adam Sherilog on Tue, Nov 2 2010
  • What is the difference? Orcad 15.7 Vs Orcad 16.3

    Presently I am using Orcad 15.7 for Capture, CIS, Pspice, ...etc. I am looking to upgrade my version. I just want to know what is the major difference between Orcad 15.7 and 16.3 in all modules (i.e., Capture, Pspice, PCB..etc). And also I want to know the cost between Orcad 15.7 and 16.3....If there...
    Posted to PCB Design (Forum) by Alexander L on Sun, Oct 31 2010
  • PSpice Parameter Sweep with X Axis Variable

    Dear All, I have one circuit of Transistor where I want to check V/I Characterstics in different values of component. For that I am using Parameter Sweep, but when I am trying to change X Axis after parameter sweep its giving some error. In normal transient simulation I am able to change the X Axis but...
    Posted to PCB Design (Forum) by Parveen on Thu, Oct 21 2010
  • Digital Centric Mixed-Signal Dynamic Power Verification – Bringing It All Together

    This is the final posting in a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will talk about concepts behind digital-centric mixed-signal verification (DMSV). My previous blogs covered some of the following topics: 1. Basics of...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 19 2010
  • CDNLive! Hot Topic – OVM-Based Verification for Analog and Mixed-Signal

    The Open Verification Methodology ( OVM ) has helped thousands of verification engineers build structured testbenches and run coverage in digital environments. Can the same advantages be leveraged to verify analog IP and mixed-signal SoCs? Yes, according to a paper planned for CDNLive! Silicon Valley...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 13 2010
  • Analog Coverage Metrics in Mixed-Signal Simulations

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 5 2010
  • CDF parameters and AMS netlister

    Hi, I'm trying to do a mixed signal simulation with AMS. In my analog design i use CDF parameters to set transistor sizes. However, the components from the tech-lib i use calculate area values from the length and width values. Because of the Ppar("var") value of the sizes, the area calulation...
    Posted to Custom IC Design (Forum) by ArjanVanHeusde on Wed, Sep 8 2010
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