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Simulation

Analog/Mixed-Signal Behavioral Modeling – When to Use What

Mixed-signal verification is a tough challenge, and much of the difficulty lies with models. How can engineers choose the right modeling approach and guarantee that models accurately represent the silicon? A session at last week's (Feb. 17) Cadence "Tech on Tour" seminar provided some answers...

Posted to Industry Insights (Weblog) by rgoering on Sun, Feb 20 2011
The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification: How good are my formal constraints? (Addressed in Part 1 ) How good is my verification proof...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Feb 14 2011
Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010), we introduced the Verification Computing Platform...

Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, Feb 14 2011
Check signal value in order to stop simulation

Hi Everyone, I am trying to optimize the simulation time but checking the value of an analog signal in the simulation. I am wondering if there is already a block (veriloga) or a function under cadence which check the value of an analog signal (i.e. for example after 10 values with 1us apart under 5%...

Posted to Custom IC Design (Forum) by frogconsultant on Mon, Feb 14 2011
NCSIM stops simulation without giving any notice.

I want to simulate a scanvector set via an instantiated scantest module in my testbench. The module takes every 8 usec a vector from the vectorset which is a seperate rom.cde file. The main part for the execution loop which is part of my verilog module is responsible for picking up a next vector from...

Posted to Functional Verification (Forum) by prkroon on Tue, Feb 8 2011
What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs, one in software, one in hardware, and one in real life. One of the reasons that corner-case conditions are missed is that some engineers don't spend enough time really thinking about their design and documenting its...

Posted to Functional Verification (Weblog) by tomacadence on Mon, Jan 31 2011
Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: " Is e or SystemVerilog Best for Constrained-Random Verification? " This blog post has received much positive feedback from other Specman...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 18 2011
What Does Silicon Realization Mean for Verification Engineers?

Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...

Posted to Functional Verification (Weblog) by tomacadence on Tue, Jan 11 2011
Infinite Playbook for the Verification Superbowl

Its 4th and long, you're down by six, the clock is running out, and you are wary of a bug-blitz. What play do you call? With new approach defined by Silicon Realization, the updated Incisive Enterprise Simulator provides the new capabilities to finsh your drive, route the bugs, and win the verification...

Posted to Functional Verification (Weblog) by Team genIES on Mon, Jan 10 2011
Q&A: Formal Verification in 2011 – Update and Forecast

Alok Jain, distinguished engineer at Cadence, directs the company's R&D efforts in formal verification. When he recently visited Cadence San Jose headquarters, we talked about the status of formal verification technology today and trends developing for 2011. Specifically, we talked about formal...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 2 2011

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Simulation

Analog/Mixed-Signal Behavioral Modeling – When to Use What

The Role of Coverage in Formal Verification, Part 3

Why the Demand for Acceleration and Emulation is Growing

Check signal value in order to stop simulation

NCSIM stops simulation without giving any notice.

What Could Be Simpler than a Request-Acknowledge Handshake?

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

What Does Silicon Realization Mean for Verification Engineers?

Infinite Playbook for the Verification Superbowl

Q&A: Formal Verification in 2011 – Update and Forecast