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Send Yourself A Copy
SimVision,Incisive
: Functional Verification
ABV
Accellera
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Mode Support for SimVision “Stop Simulation” Button
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility in the exact place where you want to pause, the...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, May 8 2013
IBM and Cadence Collaboration Improves Verification Productivity
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Wed, Feb 13 2013
Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
Posted to
Functional Verification
(Weblog)
by
Karnane
on Tue, Feb 5 2013
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision
Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, Aug 15 2012
Archived Webinar: Bringing SystemC and C/C++ Models into UVM
If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 7 2011
Specman Application Note: Improving Verification Productivity With Dynamic Load and Reseeding
Are you looking for new approaches to improve your verification productivity by 40 - 60%? Look no further... read the technical application note by Corey Goss on how to Improve Verification Productivity through Adopting Dynamic Load and Reseed Methodology. Attached is a link to the application note that...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Mar 1 2011
There's Another Simulation Failure! New SimVision Features Can Help
Simulation failures are seen quite often in design verification. Fortunately, with the new Cadence Silicon Realization approach, you'll have the tools necessary to quickly get back to simulating. The complete solution for determining what is causing your simulation to fail is SimVision, part of the...
Posted to
Functional Verification
(Weblog)
by
jimkje
on Wed, Jan 12 2011
How Do You Debug Your Testbench when it Won’t Stand Still?
The task of debugging a simulation problem in your design can be a difficult and time consuming task. These days, the verification engineer must also be able to debug very complex SystemVerilog testbenches too. This becomes difficult because of their dynamic nature -- they just won’t stand still...
Posted to
Functional Verification
(Weblog)
by
jimkje
on Tue, Dec 14 2010
DVCon: Showcasing The Cadence Passion For Verification Excellence
Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation. For all of the details, visit our DVCon events page . Highlighted below are two of...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Mon, Feb 22 2010
Demo: New Signal Tracing Capability in Incisive Enterprise Simulator
One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release. The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal tracing function in SimVision. I thought you might...
Posted to
Functional Verification
(Weblog)
by
hilker
on Wed, Oct 21 2009
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