Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Silicon Integration Initiative/Industry Insights
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Silicon Integration Initiative,Industry Insights
10th anniversary
28nm
3D IC
3D IC standards
3D: Radojcic
3D-IC
3D-IC standards
3D-ICs
Accellera
Altera
AMS
Analog
Analog Artist
architectural modeling
Arns
atomic modeling
Atrenta
Bansal
Bingham
Cadence
CCI
Chandrasekar
chip package interface
chip planning
collaboration
common power format
CPF
CPF 2.0
Custom 2.0
custom design
Custom IC
DAC
DAC 2012
Dark Silicon
DasGupta
dependency management
Design Automation Conference
design for test
DFM
DFM Coalition
DFT
Docea
DRC+
ecosystem
EDA standards
ESL
Excel
firmware
Hardee
High-level Synthesis
Hogan
Huang
IEEE 1801
IEEE 1801-2009
IEEE 1801-2013
Interoperability
low power
low power coalition
LPC
Open Access
Open3D TAB
OpenAccess
OpenAccess Coalition
OpenPDK
Palladium
Power
power formats
Sawicki
Schulz
Si2
Si2 conference
signal integrity
silicon photonics
Simulation
SoC
SoC Integration
SoC: EDA360
software
Standards
Steve Schulz
switching activity
system level
SystemC
SystemC-AMS
system-level low power
system-level power
Tan
thermal
TLM
TSVs
Unified Power Format
UPF
UPF 1.0
UPF 2.0
UPF 2.1
Varadarajan
variability
variation
variation analysis
Wang
Q&A: Qi Wang Updates EDA Power Intent Format Standards
IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 20 2013
Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 15 2012
Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling
A re we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative ( Si2 ) Conference Oct. 9, 2012, he argued that the consumer electronics marketplace will drive a new era he calls "Custom 2.0." The Si2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 11 2012
Si2 DAC Panel: What Standards are Needed for 3D-ICs?
3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 28 2012
DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess
The OpenAccess standard, which includes a common data model, API and reference database, has been one of the most successful and impactful standards in EDA history. Those who imagined, created, and continue to maintain and improve OpenAccess got some long overdue recognition June 4 at a Silicon Integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 4 2012
Renamed Si2 Conference Updates EDA Standards
The Silicon Integration Initiative ( Si2 ) standards organization has held 15 previous OpenAccess Conferences. This year Si2 is calling their annual event, scheduled for Thursday, Oct. 20, the "Si2 Conference." In addition to OpenAccess, the one-day event will provide updates on emerging standards...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 13 2011
EDA Standards Review and Forecast, Part 2 – OSCI and Si2
My last blog post provided a 2010 review and 2011 forecast for Accellera and IEEE EDA-related standards. This post looks at activity from the Open SystemC Initiative (OSCI) and Silicon Integration Initiative (Si2). Perhaps the most "newsworthy" item on this list is the 2010 emergence of the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Dec 21 2010
Si2 Speakers: EDA Standards Must Address Systems, Software
Who says standards are dull? The 15 th Silicon Integration Initiative (Si2) OpenAccess Conference opened Oct. 20 with a rousing call to action by two speakers - a call to think beyond the traditional boundaries of EDA, and to include systems and software when it comes to standards. At the same time,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 21 2010
Page 1 of 1 (8 items)