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Silicon Realization

ARM TechCon Address: High Stakes at Low Process Nodes

The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 18 2011
Whitepaper Summary: How to Succeed at 20nm

The upcoming 20nm process node promises tremendous advantages in power, performance and area - but it's also very challenging in terms of design complexity, lithography, and manufacturability. A newly published whitepaper from Cadence, summarized here, sets forth an approach that can mitigate the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 25 2011
Why Cadence Bought Azuro – A Closer Look

Cadence announced July 12 its acquisition of Azuro , a provider of "clock concurrent optimization technology" (ccopt). But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jul 24 2011
Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal and ABV

To complement our support of DAC, CDNLive, and other large scale events, where the program touches on holistic approaches to whole levels of design and verification realization , Team Verify is also proud to host the "Club Formal" event series. Patterned after the popular "ClubT"...

Posted to Functional Verification (Weblog) by TeamVerify on Tue, Jun 28 2011
Two New Resources for 3D-IC Design

Just in time for the Design Automation Conference (DAC), two new publications are providing fresh perspectives about 3D-IC design. First, the Global Semiconductor Alliance ( GSA ) has released a "3D-IC Design Tools and Services Tour Guide" for next week's DAC. Secondly, a new Cadence technical...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 2 2011
Free Webinar This Thursday: Rapid Design Bring-Up Using Formal and Simulation Together

Allow us to shamelessly promote a free webinar (including a live demo) this Thursday May 12 at 10am-11am Pacific time, entitled "Verification 1-2-3 with Assertion-Driven Simulation" . In a nutshell, in this webinar Solutions Architect Chris Komar and Product Management Director Joe Hupcey III...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, May 9 2011
How EDA360 “Realizations” Leverage Industry Standards

The EDA360 vision , articulated by Cadence one year ago, is not about one company - it's a vision for an entire industry. As such, EDA360 depends on a collaborative ecosystem with many players, including other EDA vendors, silicon IP providers, foundries, design services companies, and many others...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 9 2011
Ten Key Ideas Behind EDA360 – A Revisit

The EDA360 vision paper was published by Cadence one year ago this week. Since that time, EDA360 has been widely discussed throughout the industry - by partners and competitors alike - whether or not they actually use the term "EDA360" or just talk about the ideas behind it. Over the past year...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 28 2011
EDA360 Beyond the Chip – Package, Board, and Product Creation

The EDA360 vision , articulated by Cadence one year ago this week, calls for an expanded view of EDA that supports complete hardware/software systems ready for applications deployment. Most of the discussion during the first year focused on silicon and embedded software. A Cadence Allegro 16.5 announcement...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 25 2011

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Silicon Realization

ARM TechCon Address: High Stakes at Low Process Nodes

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

Whitepaper Summary: How to Succeed at 20nm

Why Cadence Bought Azuro – A Closer Look

Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal and ABV

Two New Resources for 3D-IC Design

Free Webinar This Thursday: Rapid Design Bring-Up Using Formal and Simulation Together

How EDA360 “Realizations” Leverage Industry Standards

Ten Key Ideas Behind EDA360 – A Revisit

EDA360 Beyond the Chip – Package, Board, and Product Creation