Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Si2
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Si2
10th anniversary
2.5D
20nm
28nm
3D
3D IC
3D-IC
Accellera
Analog
ARM
Cadence
collaboration
Common Power Format
CPF
CPF 2.0
custom design
Custom IC
DAC
DAC 2012
DAPIC
Design Automation Conference
DFM
DFM Coalition
Docea
DRC+
DVCon 2013
e language
EDA standards
EDA360
ESL
FinFET
FTAB
Genesis
Global Foundries
GlobalFoundries
GSA
GSA 3D IC
Hathaway
High-level Synthesis
Hogan
hot spots
Hsu
Huang
I Love DAC
IEEE
IEEE 1801
IEEE 1801-2009
IEEE 1801-2013
Industry Insights
Interoperability
IP
IPL
IP-XACT
Liberty
Logic Design
Low power
low power coalition
low-power
low-power design
LPC
Open Access
Open3D
OpenAccess
OpenAccess Coalition
OpenDFM
OpenLPM
OpenPDK
OSCI
Palladium
pathfinding
PCells
PDK
PDKs
Potts
Power
power formats
Python
Qi Wang
Qualcomm
Schulz
Sematech
Si2 conference
Silicon Integration Initiative
Silicon Realization
SKILL
stacked die
Standards
Steve Schulz
SystemC
thermal
TLM
TSV
TSVs
UPF
UPF 2.1
UVM
variability
Virtuoso
Wang
wide i/o
Q&A: Qi Wang Updates EDA Power Intent Format Standards
IC design teams can use one of two formats to express power intent - the Common Power Format (CPF) from the Silicon Integration Initiative ( Si2 ), or IEEE 1801 , also known as the Unified Power Format (UPF). Efforts are now underway to bring the two formats closer together, and Qi Wang, technical marketing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 20 2013
Video: What the Newly Approved IEEE 1801-2013 Low Power Format (UPF 2.1) Includes
The IEEE RevCom (Review Committee) approved a new version of the IEEE 1801 low power format, also known as the Unified Power Format (UPF), March 5. The new version is IEEE 1801-2013 or UPF 2.1. It's a significant step towards "methodology convergence" with the Common Power Format (CPF)...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 6 2013
Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 15 2012
Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling
A re we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative ( Si2 ) Conference Oct. 9, 2012, he argued that the consumer electronics marketplace will drive a new era he calls "Custom 2.0." The Si2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 11 2012
Si2 DAC Panel: What Standards are Needed for 3D-ICs?
3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 28 2012
DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess
The OpenAccess standard, which includes a common data model, API and reference database, has been one of the most successful and impactful standards in EDA history. Those who imagined, created, and continue to maintain and improve OpenAccess got some long overdue recognition June 4 at a Silicon Integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 4 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 21 2012
See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party
It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 25 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs
What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 9 2012
Q&A: OpenAccess 10th Anniversary -- A Look Backwards and Forwards
OpenAccess is one of the most successful and impactful standards in the history of the EDA industry. By providing a C++ API, data model, and reference database implementation, OpenAccess has brought unprecedented levels of integration to analog and digital IC implementation. This year OpenAccess is celebrating...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 20 2012
Page 1 of 5 (41 items) 1
2
3
4
5
Next >