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SerDes

  • Who Needs 40/100 Gigabit Ethernet SoCs?

    Short answer: the cloud. Thanks to cloud computing and cloud applications, data centers are having to manage large data transfers in very short periods of time. System-on-chip (SoC) solutions that support 40/100 Gbit Ethernet (GbE) are now in demand, and for this reason, Cadence today (Feb. 21, 2012...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 21 2012
  • Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

    IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling of SerDes transceivers. Instead of just modeling...
    Posted to PCB Design (Weblog) by Maxwell86 on Thu, Feb 11 2010
  • Brad Griffin Speaks at DesignCon - Give Him a Listen!!

    If you were not lucky enough to be atDesignCon this week, and many of us were not! You might be interested in the streaming interviews posted on line. Click here for link. Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's...
    Posted to IC Packaging and SiP (Weblog) by SiPper on Thu, Feb 5 2009
  • Allegro PCB SI at DesignCon

    Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification. In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel, Do It Right...
    Posted to PCB Design (Weblog) by Maxwell86 on Fri, Jan 23 2009
  • CDNLive! MVP discusses modeling 6 Gbps Serial Links with IBIS-AMI modeling

    Congratulations to Donald Telian and his colleagues at Hitachi and IBM on winning the Most Valuable Paper award at CDNLive! in San Jose. Donald takes you through a case study where a 6 gigabit/second Serial Attached SCSI–2 (SAS-2) interface was architected, simulated, and compliance tested using...
    Posted to PCB Design (Weblog) by Maxwell86 on Fri, Oct 3 2008
  • CDNLive! - 10 Gbit package design paper available to conference attendees

    For those of you that attended CDNLive! but may have missed the presentation on multi-gigabit package design by Kevin Roselle of Bayside Design, you can review the slide presentation by using your conference login and then downloading from here . Bayside is involved in designing many high-end packages...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Wed, Oct 1 2008
  • How stable is your IC Package's PDN?

    There are three goals for a power a delivery network (PDN): sufficiency, efficiency, and stability. Simultaneous switching of Gigahertz speed signals (i.e. DDR3) has made the stability of power a pressing issue in today’s designs. The Cadence SPB 16.2 release has addressed this challenge and will...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Thu, Aug 21 2008
  • Second Generation PCI Express spreading roots

    According to Jag Bolaria of the Linley Group, the 5 Gbps version of PCI Express has moved beyond PC applications into embedded systems and networking. In his article in DesignLine, we learn that PCIe Gen2 channels are limited to about a length of 10 inches (without connectors or vias) Take a look: PCI...
    Posted to PCB Design (Weblog) by Maxwell86 on Tue, Jul 22 2008
  • Xrosstalk talks AMI

    There's a great issue of Xrosstalk magazine out there that talks about algorthmic modeling for high speed SerDes channels. Cadence as well as other EDA companies give their take on the subject. Here's a link to the articles: http://www.xrosstalkmag.com/images/magazine/xrosstalk_magazine_june08_final...
    Posted to PCB Design (Weblog) by Maxwell86 on Fri, Jul 11 2008
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