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SerDes,IBIS-AMI,PCB Signal and power integrity

  • Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

    IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling of SerDes transceivers. Instead of just modeling...
    Posted to PCB Design (Weblog) by Maxwell86 on Thu, Feb 11 2010
  • Allegro PCB SI at DesignCon

    Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification. In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel, Do It Right...
    Posted to PCB Design (Weblog) by Maxwell86 on Fri, Jan 23 2009
  • CDNLive! MVP discusses modeling 6 Gbps Serial Links with IBIS-AMI modeling

    Congratulations to Donald Telian and his colleagues at Hitachi and IBM on winning the Most Valuable Paper award at CDNLive! in San Jose. Donald takes you through a case study where a 6 gigabit/second Serial Attached SCSI–2 (SAS-2) interface was architected, simulated, and compliance tested using...
    Posted to PCB Design (Weblog) by Maxwell86 on Fri, Oct 3 2008
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