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Schematic,Virtuoso

  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • SKILL for the Skilled: SKILL++ hi App Forms

    One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++ applications from the ground up. I.e., if you understand inheritance, you can better architect your...
    Posted to Custom IC Design (Weblog) by Team SKILL on Mon, Dec 2 2013
  • Virtuosity: 20(!) Things I Learned in June by Browsing Cadence Online Support

    Wow! There was an amazing amount of new content added last month. A lot of new videos and some Really Useful articles. Enjoy. Rapid Adoption Kits 1. CPF-AMS Low-Power Mixed-Signal Simulation CPF-AMS is an extension of mixed-signal simulation to help the designer simulate mixed-signal low-power design...
    Posted to Custom IC Design (Weblog) by stacyw on Mon, Jul 15 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Virtuoso - Wire Bus Connectivity Issue

    Hello, I am facing this issue regarding how to connect the wire bus connection to the output connectors. If you look at the attached image below I have clearly named each bus bit to its output but I am still facing error. The screenshot image displaying the error is below Any help would be appreciated...
    Posted to Custom IC Design (Forum) by sohaiba on Sun, Feb 17 2013
  • Is it possible to parameterize a Multi Bit wire with vector expressions?

    Is it possible to parameterize a Multi Bit wire with vector expressions? Also can you parameterize the number of instances in a instance defines with an iterative expressiion? I'm trying to create a schematic that you can reconfigure the number of internal devices via a parameter.
    Posted to Custom IC Design (Forum) by WesZ on Wed, Feb 1 2012
  • Complex wire labels with iterated instances

    Hi all, I'm working with the CIW version 5.10.41 and came across with the following problem when doing schematics (Virtuoso schematic composer) for a full custom mixed signal design: Let's assume that I have a 3 bit bus going into an instance (I), and I need 8 of these instances all together...
    Posted to Custom IC Design (Forum) by mtpank on Tue, Sep 27 2011
  • Thing You Didn't Know About Virtuoso: Redux

    After a long break, I'm going to try to venture back into the blogosphere, starting off nice and easy--by cheating... You see, Virtuoso IC 6.1.5 came out at the end of January, and one of the changes made to the Schematic Editor is that many of the handy dockable assistants featured in IC 6.1 are...
    Posted to Custom IC Design (Weblog) by stacyw on Wed, Apr 27 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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