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SVA

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog Behavior!

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE." Wait, aren't Property Specification Language (PSL) and SystemVerilog Assertions (SVA) digital assertion-based verification (ABV...

Posted to Functional Verification (Weblog) by TeamVerify on Mon, Mar 26 2012
Video Killed The Reference Manual Star

[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star " as you read the following] Q: What is your favorite pastime? A: Reading reference manuals! No? Really? OK -- with all due respect to our Tech Pubs team, virtually no one wants to sit down and read reference...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Jan 26 2012
Webinar Report: Power-Aware Mixed-Signal Verification

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 19 2012
Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots!

Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore. With the high quality of content and networking, it was easy to see why attendance has increased year-over-year; and why CDNLive India has become the premier conference on the region's engineering...

Posted to Functional Verification (Weblog) by jvh3 on Mon, Nov 7 2011
Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly varying clock phase timing parameters to cover the many possible combinations. A simple Verilog example...

Posted to Functional Verification (Weblog) by TeamVerify on Thu, Oct 13 2011
Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage. ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 28 2011
Webinar Seeks to “End the Debate” – e or SystemVerilog?

Which language is best for functional IC verification - e or SystemVerilog? A newly archived Cadence webinar attempts to answer this question by analyzing the key capabilities in both languages, and presenting code comparisons that show how the same functionality would be expressed in either language...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 21 2011
Re: SimVision Assertions

Hi pdar, the SVA property you paste is only evaluated at the posedge of the clk, it cannot cause a failure at the negedge of clk. When you say "SimVision Assertions" this implies that you run either our Simulator ncsim or our formal tool iev. Which? Can you share the log and waveform with us...

Posted to Functional Verification (Forum) by JoergM on Sat, Jul 30 2011

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SVA

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for Analog Behavior!

Video Killed The Reference Manual Star

Webinar Report: Power-Aware Mixed-Signal Verification

Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots!

Formal Verification with Asynchronous Clocks

Technical Tip on How to Use HDL Assertions in e

Webinar Seeks to “End the Debate” – e or SystemVerilog?

Re: SimVision Assertions