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  • Spectre XPS – Cadence Reinvents FastSPICE Simulation

    Last year I wrote a blog post suggesting that FastSPICE simulation technology is "hitting the wall." A new approach is clearly needed, and Cadence is responding this week (Oct. 9, 2013) with Spectre XPS (eXtensive Partitioning Simulator), a FastSPICE simulator that sets new milestones for speed...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 9 2013
  • TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support

    Two emerging semiconductor technologies - 16nm FinFET design and 3D-ICs - are moving closer to volume production, according to Dr. Cliff Hou, vice president for R&D at TSMC. Speaking at the TSMC Open Innovation Platform® Ecosystem Forum (TSMC OIP) Oct. 1, 2013, Hou (right) said that the EDA and...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 7 2013
  • Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says

    SANTA CLARA, Calif.--Just a few hundred yards from twisting and turning amusement park roller-coasters, Martin Lund took his audience on another thrill ride on Tuesday morning: a journey through the state of today's semiconductor memory business. For decades, that semiconductor memory business--primarily...
    Posted to The Fuller View (Weblog) by Brian Fuller on Tue, Aug 6 2013
  • MemCon Panelists Chart Future of Semiconductor Memory

    Density, power, bandwidth, latency - all of these memory attributes will improve during the next few years, according to panelists at the MemCon 2012 conference Sept. 18. But don't underestimate the challenges, don't expect to replace NAND and DRAM, and forget about the dream of a "universal"...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 26 2012
  • MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem

    Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 18 2012
  • FPGA PCB design considerations

    Hi, I am currently working on a data acquisition system that includes an ADC, a SRAM memory chip and an FPGA. The main idea here is to sample the waveforms with the ADC, feed the data to the memory chip, then use the FPGA and some USB device to send the data from the memory chip to the FPGA and then...
    Posted to PCB Design (Forum) by Lambros on Mon, Apr 18 2011
  • ARM Keynote: Some Inconvenient Truths About Low-Power Design

    While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 17 2011
  • SNM calculation for SRAM

    Hey, I am currently working on SRAM cell. I need to calculate the SNM-read, write and idle for my cell. I have the understanding of what is SNM. But i am not sure on how to plot the butterfly curve for the cell in cadance. Could any1 please help me with this. Thank you Mohana
    Posted to RF Design (Forum) by Mohana on Mon, Dec 6 2010
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