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SPICE,Industry Insights
106.1.0
14nm
14SOI
16nm
20nm
3D
3D transistor
3D transistors
Altos
AMS
AMS Designer
AMSmadeEZ
Analog
analog assertions
analog designers
analog IP
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analog/mixed-signal
Applicon
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ARM
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Babbage
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BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor
A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without an accurate compact model. Fortunately, the BSIM-CMG model available from the University of California...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 21 2013
Is Fast SPICE Simulation Hitting a Wall?
The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed. So-called "Fast SPICE" simulators can provide considerable speedups -- but current Fast SPICE...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 19 2012
Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm"
Few people have been as influential in the development of EDA as Alberto Sangiovanni-Vincentelli , professor at the University of California at Berkeley and Cadence board member. At the International Conference on Computer-Aided Design (ICCAD ) Nov. 6, he delivered a presentation that ranged from the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 8 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 31 2012
Keynote: From “Tribulations” to Mixed-Signal Success at Texas Instruments
Texas Instruments has experienced many "tribulations" in mixed analog and digital design, according to Chris Collins, a director at Analog Design Services at TI. But significant progress is underway. At a keynote speech at the recent Mixed-Signal Technology Summit held at Cadence Sept. 20,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 26 2012
User View: A 20nm Custom IC Constraint-Driven Flow
If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 25 2012
FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges
At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 23 2012
Digital and Analog Verification – Round Peg in a Square Hole?
Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 9 2012
Webinar Report: Power-Aware Mixed-Signal Verification
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions
Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 19 2012
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