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SOC Encounter

  • non-clock tree cells on clock tree paths

    Hello, I have a question regarding the use of non-clock tree cells on clock tree paths. The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths. During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements...
    Posted to Digital Implementation (Forum) by chris06 on Fri, Jun 13 2014
  • SOC Encounter producing functionality error

    Hi all, I've ran into a particularly a troublesome error while running SOC Encounter. I'm currently implementing a design starting from behavioral verilog, synthesizing using Design Compiler and then running place and route using SOC Encounter. The problem is that the verilog netlist produced...
    Posted to Digital Implementation (Forum) by fieldy on Fri, Feb 28 2014
  • LVS verification for gds file from Cadence SOC Encounter

    Hi, How to verify the LVS for gds file from Cadence SE. I have used 65nm STM standard cells for generating netlist file for layout and schematic design. i am getting mismatch erros in Calibre LVS report (INCORRECT). How to avoid bulk pins (vdds, gnds) in schematic, and missing instance (nsvtlp, psvtlp...
    Posted to Digital Implementation (Forum) by FMRLI on Sat, Jan 18 2014
  • UltraSim simulation issue for Power-up Rush Current Analysis with Power Gate(Switch)

    Hi All, I'm trying to run a rush current Analysis for a power-gated design I am implementing. I've been going through the Encounter and EPS manual to set the analysis up properly and I don't think I'm doing anything wrong...But whenever I run the power-up (rush current) analysis, EPS...
    Posted to Digital Implementation (Forum) by fieldy on Wed, Sep 25 2013
  • Re: Clock Tree Synthesis - Not able to add clock buffers

    I have reattached a new cts report. I cannot understand why the actual Max. Rise Sink tran and Max. Fall Sink Tran are so big (would this problem arise from incorrect library characterization?). Please see the attached file for more details. Actual Max. Rise Sink Tran : 391862(ps) Actual Max. Fall Sink...
    Posted to Digital Implementation (Forum) by Northfork on Thu, Apr 25 2013
  • optDesign command in SoC Encounter

    Hi all, I was wondering if there is a way to disallow the movement of cells by the optDesign command in SoC Encounter. I have two power domains, where one power domain contains cells that are power gated (rails are virtual vdd and gnd) and the other power domain has nominal supply. However, when I run...
    Posted to Digital Implementation (Forum) by Northfork on Sun, Apr 21 2013
  • Automating SOC Encounter Timing Optimization

    Hi All, I have a couple of questions on running SOC Encounter. My goal is to run the encounter using a tcl script and be able to have a flow that runs through all the necessary steps by running the script, instead of having to use the GUI. 1. Does anybody know a good way (or if it is even possible) to...
    Posted to Digital Implementation (Forum) by fieldy on Thu, Mar 21 2013
  • checkRoute

    When i do checkRoute..following message is seen "several (1) nets have antennas or data inconsistencies all 1074695 nets 4581405 terms of cell top_design are properly connected" So can any one explain this........??
    Posted to Digital Implementation (Forum) by ArvindBezawada on Sat, Dec 8 2012
  • How to add tap cells

    Hi, I want to add tap cells manually around a placement blockage. So can any 1 help me out how to do this Like how to call in the tap cells within the design and place them like a macro around the blockage and freeze their location Or is there any other better way to do this. Would appreciate if any1...
    Posted to Digital Implementation (Forum) by Anuragjn on Mon, Oct 8 2012
  • Hold violation at post P&R simulation

    Hello, I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit...
    Posted to Functional Verification Shared Code (Forum) by shahein on Sun, Oct 7 2012
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