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RTL,Logic Design

  • 8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

    It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
    Posted to Logic Design (Weblog) by David Stratman on Mon, Jun 20 2011
  • What Madonna Can Teach You About Chip Design

    Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other 1980's pop stars can still sell out arenas...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Mar 26 2010
  • When Will We Move From RTL to TLM? I Need to Know!

    My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Mar 8 2010
  • How-to Plans for ECOs - Advice From Experts

    By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive...
    Posted to Logic Design (Weblog) by Team FED on Thu, Oct 15 2009
  • Where Oh Where is "number_of_routing_layers"?

    OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
    Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009
  • Leveraging Silicon Virtual Prototyping Technology in Synthesis

    How many times has this happened to you? The wireload model based timing engine in your synthesis tool indicates that you have finally closed the timing on your design. You can now hand the design off to the back end implementation engineer and focus on your other tasks. A week or two go by and you get...
    Posted to Logic Design (Weblog) by mrardon on Mon, Nov 17 2008
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