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RTL compiler,tcl

  • Virtual Clock and Synthesize :)

    Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...
    Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
  • command line arguments into RC tcl scripts

    Hi, Is it possible to pass command line arguments (similar to argv in normal tcl scripts) into RC tcl scripts? What I understand is that, when RC is invoked with a '-f' option it invokes the script in its own shell and then invokes the script specified. Supposing that for example, within this...
    Posted to Digital Implementation (Forum) by kasyab on Wed, Sep 8 2010
  • How to blast a selected busse in RC ?

    I have defined in my design a bus wire. In the corresponding verilog it is seen as : wire [3:0]MyBusWire How can I blast this wire in RC ? The nets will become : wire MyBusWire_0, MyBusWire_1, MyBusWire_2, MyBusWire_3; Of course I want to keep all my other busses unblasted ! Patrick.
    Posted to Logic Design (Forum) by PatBoug on Wed, Aug 18 2010
  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!

    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010
  • Re: RE: How to count number of paths in RTL-compiler group?

    Again you helped me very much Johannes! Thanks a lot! One minor correction in order that code work correct. Line if {$TMP eq "No paths found"} { should be replaced with if {$TMP eq "No paths found."} { i.e. dot must be added to expression.
    Posted to Logic Design (Forum) by dkos on Fri, Nov 28 2008
  • Re: How to count number of paths in RTL-compiler group?

    Thanks for answer Johannes, This solution works. And do you have an idea how to detect if path group empty or not in tcl script? Let me clarify my problem a little: I automatically create cost groups between all clocks in design in script. If there are 2 clocks in design my script will create following...
    Posted to Logic Design (Forum) by dkos on Thu, Nov 27 2008
  • How to count number of paths in RTL-compiler group?

    Hello all! Does anybody knows how to count number of paths in group, created by 'path_group' command? Or, at least, determine is group empty or not? Thanks, dkos
    Posted to Logic Design (Forum) by dkos on Tue, Nov 25 2008
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