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RTL compiler,DVFS

  • Designer View – Low-Power IC Design Challenges and Solutions

    The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
  • When Do You Know You've Saved Enough Power?

    This guest post is by David Weir, Lead Design Engineer at Cadence. His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley. In this paper we set out to show how designers can measure and explore the impact of implementing...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 2 2009
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