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RTL compiler,Altos Liberate

  • Set default load in Library generation

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler uses a a load I am unaware of . Is is possible for me to generate library file which defines a default load to all pins unless stated ? . 2...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Default Load in RTL Compiler

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler does produce a result but I am uncertain of which load it is assuming d what toggle rate or stimuli is being considered... . 2) I want to set...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Library Generation

    Hallo, I am creating a standard cell library. Should I generate Netlist including the load caps the schematic. if at all does it make any difference, including and ignoring load cas in Netlist used in Library generation.
    Posted to Custom IC Design (Forum) by GreenGraphene on Mon, Mar 25 2013
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